1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various methods of forming substantially defect-free, fully strained silicon-germanium fins for a FinFET semiconductor device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A conventional FET is a planar device that typically includes a source region, a drain region and a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the past decades. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed and in lowering operation currents and voltages of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device A that is formed above a semiconductor substrate B. The device A includes three illustrative fins C, a gate structure D, sidewall spacers E and a gate cap layer F. The gate structure D is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material, and one or more conductive material layers that serve as the gate electrode for the device A. In this example, the fins C are comprised of a substrate fin portion C1 and an alternative fin material portion C2. The substrate fin portion C1 may be made of silicon, i.e., the same material as the substrate, and the alternative fin material portion C2 may be made of a material other than the substrate material, for example, silicon-germanium. The fins C have a three dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device A when it is operational. The portions of the fins C covered by the gate structure D are the channel regions of the FinFET device A. In a conventional process flow, the portions of the fins C that are positioned outside of the spacers E, i.e., in the source/drain regions of the device A, may be increased in size or even merged together (not shown in FIG. 1A) by performing one or more epitaxial growth processes. The process of increasing the size of or merging the fins C in the source/drain regions of the device A is performed to reduce the resistance of source/drain regions and/or make it easier to establish electrical contact to the source drain regions.
In the FinFET device A, the gate structure D encloses both sides and the upper surface of all or a portion of the fins C to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride is positioned at the top of the fins C and the FinFET device only has a dual-gate structure (sidewalls only). Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to increase the drive current per footprint of the device. Also, in a FinFET, the improved gate control through multiple gates on a narrow, fully-depleted semiconductor fin significantly reduces the short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins C, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction. In a FinFET device, the “channel-width” is estimated to be about two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance, capability and reliability of such devices. Device designers are currently investigating using alternative semiconductor materials, such as so-called SiGe, Ge and III-V materials, to manufacture FinFET devices which are intended to enhance the performance capabilities of such devices, e.g., to enable low-voltage operation without degrading their operating speed.
However, the integration of such alternative materials on silicon substrates (the dominant substrates used in the industry) is non-trivial due to, among other issues, the large difference in lattice constants between such alternative materials and silicon. That is, with reference to FIG. 1A, the lattice constant of the alternative fin material portion C2 of the fin C may be substantially greater than the lattice constant of the substrate fin portion C1 of the fin C. As a result of this mismatch in lattice constants, an unacceptable number of defects may be formed or created in the alternative fin material portion C2. As used herein and in the claims attached hereto, a “defect” essentially refers to a misfit dislocation at the interface between the portions C1 and C2 of the fin C or threading dislocations that propagate through the portion C2 on the fin C at well-defined angles corresponding to the (111) plane.
With respect to forming such lattice-mismatched materials on one another, there is a concept that is generally referred to as the “critical thickness” of a material. The term “critical thickness” generally refers to materials that are in one of three conditions, i.e., so-called “stable,” “metastable” or “relaxed-with-defects” conditions. These three conditions also generally reflect the state of the strain on the material. That is, a stable material is in a fully-strained condition that is 100% strained in at least one crystalline plane of the material.
FIG. 1B is a graph taken from an article entitled “Silicon-Germanium Strained Layer Materials in Microelectronics” by Douglas J. Paul that was published in Advanced Materials magazine (11(3), 101-204 (1999)). FIG. 1B graphically depicts these three conditions for blank (unpatterned) silicon-germanium materials (Si1-xGex; x=0-1). The vertical axis is the critical thickness in nanometers. The horizontal axis is the concentration of germanium in the silicon-germanium material. At the leftmost point on the horizontal axis is pure silicon (Ge concentration equals 0.0). At the rightmost point on the horizontal axis is pure germanium (Ge concentration equals 1.0). The two curves R and S define the stable, metastable and relaxed-with-defects regions for silicon-germanium materials having differing germanium concentration levels. Above and to the right of curve R are materials that are in the relaxed-with-defects condition. Below and to the left of the curve S are materials that are in the stable condition. The region between the two curves R and S defines the region where materials are in the metastable condition.
With reference to FIG. 1B, a layer of pure germanium (Ge concentration equal to 1.0) may be in the stable condition at a thickness up to about 1-2 nm (point CT1) and it may relax beyond about 4 nm (point CT2). Between about 2-4 nm, germanium is in a so-called “metastable condition” meaning it can easily relax if it is subjected to a relatively high temperature anneal. In contrast, a layer of silicon-germanium with a 50% concentration of germanium may be in the stable condition at thicknesses up to about 4 nm (point CT3) and it may be in a metastable condition for thicknesses between about 4-30 nm (point CT4). Above a thickness of about 30 nm, a layer of silicon-germanium with a 50% concentration of germanium will be in the relaxed-with-defects condition.
A material that is in the relaxed-with-defects condition is a material that contains visible defects that are indicative that the material has relaxed to the point where defects have been formed in the material. For example, FIG. 1C is a TEM photograph of a cross-sectioned fin of a FinFET device (taken along the axial length “L” of the fin) wherein the substrate fin C1 is comprised of silicon and the alternative fin material portion C2 of the fin is comprised of silicon-germanium with a 50% concentration of germanium (SiGe0.5). The axial length direction “L” and height direction “H” of the fin are indicated in FIG. 1C. In this example, the thickness or height “H” of the alternative fin material C2 was about 30 nm, a thickness greater than the metastable critical thickness for the blank (unpatterned) growth of this material (which is about 30 nm according to FIG. 1B). Accordingly, the alternative fin material C2 is in the relaxed-with-defects condition and defects are visible throughout the alternative fin material C2 and at the interface between the materials C1/C2. Thus, in the example, the alternative fin material C2 shown in FIG. 1C is fully relaxed in all three directions—axial length L, height H and width W, i.e., it is in the relaxed-with-defects condition.
The presence of defects in an alternative material fin structure would be detrimental to device operations. One process that has been investigated for use in forming such alternative fin materials is known as aspect-ratio-trapping (ART). In general, the ART process involves forming a masking layer, such as silicon dioxide, above a semiconductor substrate, such as silicon, patterning the masking layer to define a trench that exposes the underlying substrate, and performing an epitaxial growth process to form an alternative fin material, e.g., silicon-germanium, on the exposed substrate, wherein the growth is confined within the trench. That is, the ART process involves epitaxially growing fully relaxed, unstrained material hetero-structures in a high aspect-ratio silicon dioxide trench having an aspect ratio of 5 or greater in an attempt to decrease defects. In some applications, the ART process may involve the formation of trenches that have a very high aspect ratio, e.g., about 25-30. Importantly, in the ART process, the trench is made deep enough such that defects generated in the alternative fin material will be trapped at or near the bottom of the original trench and in the sidewalls of the trench positioned slightly above the interface between the substrate material and the alternative fin material. The amount of defects generated and the propagation of such defects will depend upon the crystal orientation of the substrate. The intent of the ART process is that, while the defect-containing fin material is present at or near the bottom of the trench, the upper-most portions of the epitaxially grown alternative fin material will be substantially defect-free material but, importantly, it is an un-strained material. That is, the alternative fin material is fully relaxed in all crystalline planes, e.g., in the crystalline planes that correspond to the axial length direction, height direction and width direction of the fin. This occurs due to the “trapping” of the defects at or near the bottom of the trench, with the result being the formation of substantially defect-free alternative fin material above the defective-containing portions of the alternative fin material in the lower portion of the trench. In principle, the ART process does not present a limitation with respect to the thickness of the lattice-mismatched layer, which is typically fully relaxed, a few 100 nm thick, and with defects intentionally confined close to the bottom interface. The defects are generated along the (111) crystallographic direction of the alternative fin material and they are captured or stopped by the sidewalls of the trench.
In one particular example, as it relates to the formation of P-type FinFET devices, device designers have investigated the use of pure germanium and silicon-germanium, along with a high uniaxial compressive stress, as the fin material so as to improve charge carrier (i.e., holes) mobility in the devices. To be effective, the germanium or silicon-germanium fin material will ideally be formed in a highly-strained, substantially defect-free condition. Several prior art techniques have been attempted in an effort to form such materials, e.g., blanket growth of a germanium or silicon-germanium material on a stress relaxation buffer layer having an intermediate lattice constant between the fin material and the silicon substrate, cladding processes, cladding plus condensation thermal treatment, replacement fin techniques, etc. Unfortunately, the prior art techniques have yet to be able to form highly-strained, substantially defect-free germanium or silicon-germanium in a sufficient thickness so that it may be used in actual devices. In addition, many of the above-mentioned prior art processing techniques are generally incompatible in terms of the thermal budget required to practice the conventional Si baseline integration flows on bulk substrate materials.
The present disclosure is directed to various methods of forming substantially defect-free, fully strained silicon-germanium fins for a FinFET semiconductor device that may solve or reduce one or more of the problems identified above.